Decoupling/bypass capacitors are employed in a variety of signal processing applications such as telecommunications, instrumentation, computers, and integrated circuits in general. Typically, because of the size limitations on the packaging of these systems and components, such capacitor elements are housed in a monolithic structure having a size and shape that is readily adaptable to a broad spectrum of circuit mounting configurations. One such configuration, commonly termed a bar-cap, shown diagrammatically in FIG. 1, contains an array 10 of capacitor elements 11-1, . . . , 11-N integrated into a ceramic strip 12 that readily lends itself to attachment to a number of different structures and devices including reduced size packaging elements such as leadless chip carriers, as diagrammatically depicted in FIG. 2. As shown therein, because of its very small dimensions (a width W on the order of 0.02-0.04", a length L on the order of 0.06-0.125" and a thickness T on the order of 0.007") one or more (e.g. a pair 21 and 22 being shown in FIG. 2) bar-caps can be situated immediately alongside a semiconductor chip 23, so as to facilitate minimum distance connections between conductors on the chip and top plates 15 of respective capacitors of the barcaps 21,22.
Now, even though a bar-cap configuration offers a microminiaturized packaging design that has gained wide acceptance from a standpoint of its small size and integration density, as the bandwidths and signal processing speeds of circuit components and systems continue to increase, its operation and, consequently, its useful performance as a bypass/coupling element become impacted by the presence of parasitic capacitive coupling through the ceramic substrate between the top plates of the respective capacitor elements of the bar-cap.
More particularly, with reference to FIG. 3 there is diagrammatically illustrated a side view of a typical physical configuration of a bar-cap together with electrical circuit equivalents of the components the bar-cap is intended to provide. As shown therein, for an exemplary six capacitor bar-cap array, a ceramic substrate 31 has a first surface 32 on which are distributed a plurality (six) of first or top plate electrodes 33-1, . . . , 33-6 and a second or bottom surface 34 on the entirety of which a reference plane conductor layer 35 is formed. Through the medium of the ceramic substrate a plurality of capacitors 41-1, . . . , 41-6 are monolithically integrated within the bar-cap between top electrodes 33 and bottom electrode 35. The bar-cap is normally attached to an associated packaging structure such that layer 35 is mounted atop a ground plane conductor. Also schematically illustrated in FIG. 3 are a plurality of parasitic interelectrode capacitors 45 that are formed in upper surface regions of the substrate 31 between respective ones of the top electrode segments 33. For high bandwidth - high signal processing speed applications and materials (e.g. GaAs), these interelectrode capacitances may circumvent the intended decoupling of the elements of the bar-cap and actually intercouple signal lines to which the top electrodes are connected, thereby defeating the effectiveness of the bar-cap.